The reduced instruction set RISC is a legend in the history of the development of computer chips. Its most proud work is that in 1983, Acorn Company of the United Kingdom launched the Acorn RISC Machine (ARM), a new processor architecture research and development project based on the RISC project concept of the University of California, Berkeley. This is the beginning of the ARM architecture that now dominates mobile chips. Berkeley's RISC project developed four generations in the 1980s, and in 2010 launched the fifth generation design, namely RISC-V.
RISC-V is an instruction set, not a processor implementation. The instruction set is a standard specification, which is equivalent to an agreement of everyone. If you follow the same standard specification, then software and hardware produced by different manufacturers can work together, just like the size specification of screw and nut.
With the instruction set standard specification, the most important next step is chip design. Complete the design of the micro-architecture according to the instruction set, form a document, and then form the source code through engineering development. After you have the source code, you can use EDA software to form a chip layout, and finally hand it over to foundries such as TSMC or SMIC for tape-out to realize chip manufacturing.
When many people focus on the manufactured equipment or the designed software, it is easy to quietly ignore the invisible "microarchitecture design and implementation". In fact, this is a very important capability and the core competitiveness of chip design.
When you have the ability to design and implement microarchitecture, you will no longer be limited by the instruction set. If you want to change an instruction set, it will be very easy. In the past few decades, the performance of Intel processors has been continuously improved. What is the reason? The increase in the instruction set is certainly a visible accumulation, but more importantly, the continuous evolution of Intel processor micro-architecture and technology. Starting from Intel's P6 architecture in 1995, to 2000 and then to 2006, the architecture will evolve every five years. In the process of continuous iteration, the optimization at the micro-architecture level is realized. And that's at the heart of Intel's design capabilities. Even from this point of view, the instruction set is somehow not that important, because it is just a standard specification. The design and implementation capabilities of the microarchitecture really determine the performance, power consumption, and area of a chip.
Apple has changed multiple instruction sets over the past few decades, from Motorola to Intel, to PowerPC, and today to ARM. Due to Apple's own strong vertical collaborative design capabilities, it is not too difficult to replace the instruction set. The domestic Loongson company, because of its strong chip design capabilities, hardly needs to make too many changes in the microarchitecture design when switching from the MIPS instruction set to its own instruction set Loongson (longArch) instruction set. There are also companies in China that are developing designs that can support Arm and RISC-V at the same time, because the underlying micro-architecture design does not require major changes to support different instruction sets.
Despite the significance of RISC-V, there are still many misconceptions in the industry. In December 2022, Professor David Patterson wrote an article specifically to correct some fallacies about RISC-V.
The first misunderstanding, RISC-V is an open source processor, just like Linux is an open source operating system. In fact, RISC-V is not an open source processor, it is just a standard specification, essentially a descriptive manual, similar to Ethernet standards, USB standards, etc. The Linux operating system is a source code. So the two are not comparable. RISC-V is a standard, and the International Foundation is like a working group that develops standard specifications.
The second misunderstanding is that a mature and closed instruction set is safer and more reliable than an open instruction set. Security has nothing to do with closed versus open source. The closed instruction set belongs to the company, and it will be closely bound to the fate of the company. If the company is in a downturn, the company's instruction set will disappear, and the security of the supply chain will not be guaranteed. There are many instructions that have disappeared in history, including the once popular DEC VAX and DEC Alpha instruction sets. In addition, the closed instruction set may not be stable. At that time, MIPS was sold to six companies, and ARM also had three owners. Changing one owner means that the business model may change.
The third misunderstanding is that the closed instruction set is uniform and there is no fragmented state. In fact, closed instruction sets often encounter unforeseen incompatibilities during their lifetime. Even under one system of ARM, there have been incompatibilities. ARMv1 to ARMv7 use a 32-bit address space. However, ARMv8-a, which can provide both 32-bit and 64-bit address versions in the next generation, is not compatible. Moreover, ARMv8-a and ARMv8-m are not compatible even if they are of the same generation. Fragmentation is actually a normal state to some extent.
The fourth misunderstanding, compared with the closed instruction set, the modularization of RISC-V has led to a more fragmented software ecosystem. At this point, the RISC-V technical working group is already providing some new mechanisms, such as the configuration (Profile) mechanism, to standardize the software ecosystem, so that the software will not be as fragmented as imagined.
The last fallacy, many people assert that RISC-V cannot become a mainstream instruction set. It is too early to draw conclusions on this point. Technically speaking, RISC-V can support the fields from embedded, to ordinary computers, to supercomputers, and there are no systematic defects. From a commercial point of view, more open standards tend to be more viable. This is comparable to the success of the Linux operating system.
Five major trends of RISC-V
RISC-V has begun to develop into the high-performance field. In the past, many people thought that it could only be used in the embedded field, but in recent years, a batch of RISC-V high-performance processors have emerged, representing companies such as Sifive and Ventana in Silicon Valley, which have certain advantages in technology.
There are also Xiangshan processors in China, as well as Shanghai Saifang. SiFive has recently launched a RISC-V processor up to 3.4GHz. Its performance can be compared to ARM A78, which is a very high-performance processor. Compared with the domestic market, in terms of research and development progress, this design is about a year ahead of the domestic Xiangshan. But Xiangshan also has its advantages, because Xiangshan cooperates with multiple companies to develop through an open source and open model, which can iterate faster and reduce costs through sharing.
It is worth noting that many countries are actively promoting or supporting RISC-V at the national level. For example, in June 2022, the Russian Ministry of Digital Development announced that it will vigorously support the development of RISC-V processors. India has also launched the "Digital India RISC-V Processor" (DIR-V) Development Plan".
At the same time, the Ministry of Electronic Information of India (equivalent to the Ministry of Industry and Information Technology in China) joined the RISC-V International Foundation in the name of the Ministry and became a senior member. In addition, on September 8, 2022, the European Union released the "Proposal and Roadmap for Establishing European Open Source Hardware, Software and RISC-V Technology Sovereignty" report, supporting RISC-V and open source hardware, especially giving nine priority developments The key directions are given, and the implementation path is given, including the establishment of non-profit institutions to support research and development, the implementation of educational policies and measures, and so on. It can be seen that the whole world is actively investing in RISC-V ecological construction.
The development of the RISC-V key software ecosystem is also very rapid. On the one hand, the RISC-V International Foundation is actively promoting the adaptation of basic software; on the other hand, many open source software communities are also actively adapting. This makes software forces all over the world support the development of the RISC-V ecosystem. Taking the Linux distribution Debian as an example, the open source community began to support RISC-V in 2019. With the efforts of the open source community around the world, 95% of the more than 20,000 software packages were transplanted in just three years, making RISC -V becomes the Tier-1 architecture supported by Debian. In terms of RISC-V ecological construction, China is in the first echelon. Especially since 2018, many companies are launching various RISC-V-based chip products. At the same time, local governments have also issued a series of policies. The Beijing government, in particular, has invested heavily in RISC-V.
As the RISC-V software ecosystem is also accelerating, RISC-V is being supported by more and more companies. In addition to startups, giants such as Intel are also actively investing in the ecological construction of RISC-V. American companies have invested heavily in the field of high-performance processors and are generally in a leading position. But in China, start-up companies are very active, and the number is much larger than that of the United States. Although at present, it is still mainly concentrated at the MCU level. But this has injected a little fresh air into the monopolized markets of Europe, America and Japan.
Overall, RISC-V applications are growing rapidly around the world. In the first half of 2022, data from the RISC-V International Foundation shows that the shipment of RISC-V has exceeded 10 billion, and it is expected to exceed 80 billion by 2025. Generally speaking, RISC-V still lacks some milestone and benchmark RISC-V applications. But the good news is that the European Union plans to invest 270 million euros to develop supercomputers, which will be a milestone event.
